In general, the production of interconnect tracks in integrated circuits includes, for each metallization level, the deposition of a metal layer on a thick insulating layer. The insulating layer, for example, may be a layer of silicon dioxide having a thickness of 6000 .mu.. The deposition is followed by etching, generally plasma etching, of the metal layer to obtain a track having a predefined width and a predefined length.
Those skilled in the art know that, during this etching operation, electric charges are deposited on the metallic segments. Now, in some cases, such a metal segment may be connected to the insulated gate of an insulated-gate field-effect transistor (MOSFET transistor) and have its other end free, i.e. not connected to another component. Such a connection is then called a "floating" connection. If the length of this floating connection is too great, the amount of charge deposited on the corresponding metallic segment, which is proportional to the length of the latter, will create too great of a flow of charge through the gate oxide. The gate oxide is a thin oxide, and the flow of charge may lead to a degradation of the performance characteristics of the transistor quite quickly and quite suddenly.
Special rules for designing such interconnect tracks, known to those skilled in the art by the name "Antenna rules", are therefore defined. These rules include the creation of discharge paths for the electric charges accumulated on the metallic segments. For example, provision may be made for the gate of a MOSFET transistor to be connected to a discharge diode formed, for example, by the source region or by the drain region of another MOS transistor or else by a specific region produced in the semiconductor substrate. Furthermore, in the absence of a protective diode, these rules define a maximum ratio between the area of metal of a floating connection and the area of the gate of the transistor. In practice, given that the widths of the gates and the widths of the tracks are identical, a critical length L.sub.c is defined which a floating connection must not exceed. This critical length L.sub.c is typically about 200 times the length of L.sub.G of the gate.
When an interconnect track connects the gate of an MOS transistor to a discharge diode on only one metallization level, the problem mentioned above does not arise. This is so because during the operation of etching the interconnect track, the connection is not floating, and the electric charges are removed in the discharge diode.
The problem mentioned above arises for an interconnect track connecting the gate of an MOS transistor to a discharge diode on at least two metallization levels, with a track element extending under the highest metallization level and having a length greater than the critical length.
When the general design diagram of the integrated circuit, i.e. the diagram indicating the position of all the components of the integrated circuit and the geometrical configuration of all the interconnect tracks, has been defined, generally by means of a CAD tool, and when such a general design diagram reveals an interconnect track whose geometrical characteristics are in violation of the antenna rules defined above, a conventional approach includes modifying the initial geometrical configuration of such an interconnect track. For example, it may be modified by "praising" it vertically within the integrated circuit so as to reach a higher metallization level allowing direct connection to the discharge diode. Apart from the fact that such an approach requires manual modifications on a case-by-case basis, it also leads to integrated circuits which may be more complicated to produce than those initially provided and may not have the desired maximum compactness.
Another approach may include systematically using components comprising a MOSFET transistor and a discharge diode in the immediate vicinity of this transistor so as not to violate the above-defined antenna rules. However, such an approach would lead to a significant increase in the area of the integrated circuit.